FPGA work

Programmable logic blocks, timing checks, and deterministic IO.

The FPGA side of the lab focuses on practical prototype logic: capture paths, timing adaptation, control IO, board bring-up, and component choices that make the design buildable.

FPGA prototype validation bench with oscilloscope probes and ADC front-end board. — FPGA validation plate / timing, acquisition, and IO

Bench setup

Logic work tied to measurements, traces, and board-level reality.

FPGA validation is presented as a measured workflow: clocks, interfaces, capture paths, control timing, and correlation with physical test equipment.

Timing constraints and clock-domain review
ADC/DAC capture and buffering paths
Logic analyzer and oscilloscope correlation

Representative work

FPGA-DAQ

Multi-channel acquisition core

Synchronized ADC sampling, timestamping, buffering, and USB/Ethernet streaming for compact measurement devices.

FPGA fabric / ADC front end / timing PLL / host bridge

FPGA-MOTION

Deterministic motor-control IO

Low-latency PWM, encoder capture, fault input handling, and isolated gate-driver evaluation for control prototypes.

PWM logic / quadrature decode / isolation / MOSFET drivers

FPGA-VISION

Camera preprocessing pipeline

Sensor bring-up, parallel video capture, line buffering, pixel transforms, and measurement hooks for edge-vision devices.

MIPI-style IO study / frame buffers / debug probes

FPGA-LINK

Protocol bridge and timing adapter

Bridges between legacy parallel buses, SPI, LVDS-style links, and microcontroller hosts where firmware alone is too slow.

Bus bridge / clock domains / CDC checks / logic analyzer traces

FPGA validation focus

Clock-domain crossing review

ADC/DAC capture and buffering

Low-latency control paths

Parallel bus and protocol bridges

Logic analyzer and oscilloscope correlation

HDL test benches and bench notes